Recent information processing apparatuses such as a server computer often include a service processor. The service processor is an independent computer for performing remote control and management of operations of the entire information processing apparatus including a CPU (Central Processing Unit) serving as a processor. For example, the service processor performs emergency control when the server computer is in trouble, and performs starting/stopping at normal time.
A conventional information processing apparatus including a service processor will be described with reference to FIG. 9. FIG. 9 is a diagram illustrating an example of a conventional server computer including a service processor. For example, a server computer 900 includes a CPU 902 and a service processor 901, which are connected by a reset signal line 905. The CPU 902 is further connected to an SDRAM (Synchronous Dynamic Random Access Memory) 903 which is a volatile main storage device. The CPU 902 is connected with a boot ROM (Read Only Memory) 904 by a bus 906. The SDRAM 903 is an SDRAM group including a plurality of SDRAMs. The boot ROM 904 contains a boot firmware program.
The CPU 902 includes one or more cores 921 to be recognized as a single processor by a program, and a cache 922 for the SDRAM 903. The CPU 902 is connected to an IO (Input Output) controller 907 and a network interface controller 909 by a bus. The IO controller 907 is connected with an external storage device 908 such as a hard disk.
The server computer 900 performs a system reset and boot, for example, by the following procedure. The service processor 901 inputs a reset signal to the CPU 902 via the reset signal line 905. Specifically, the service processor 901 inputs 0 to the CPU 902 other than when inputting the reset signal. When inputting the reset signal, the service processor 901 changes the value input to the CPU 902 to 1. The service processor 901 then restores the value input to the CPU 902 to 0 to cancel the reset signal, and inputs an execution instruction to reset the CPU 902 to the CPU 902.
All the core(s) 921 included in the CPU 902 receive(s) the input of the reset execution instruction from the service processor 901. All the core(s) 921 start(s) an instruction fetch from a fixed address in the boot ROM 904, to which fixed physical address are assigned, and an execution instruction for startup processing. The fixed address is also referred to as a reset address.
Here, the cache 922 built in the CPU 902 operates as an SDRAM device that is accessed in a non-cacheable manner and to which fixed physical addresses are assigned.
A boot firmware program 941 serving as a program for booting the server computer 900 is stored in the reset address in the boot ROM 904. When the reset signal is cancelled, the CPU 902 executes the boot firmware program 941 stored in the boot ROM 904.
The CPU 902 executes the boot firmware program 941 to perform the following processing. Initially, a POST (Power On Self-Test) is performed to do an operation test inside the CPU 902. Next, if serious failures are not detected by the POST and operations can be continued, the SDRAM 903 is initialized and refreshing of the SDRAM 903 is started. The SDRAM 903 hereafter retains written data and operates as a main storage device. Next, the boot firmware program 941 is copied to the SDRAM 903. A data area to be used by the boot firmware program in the SDRAM 903 is initialized. The operation mode of the server computer is then changed to a mode where the cache 922 included in the CPU 902 operates as a cache of the SDRAM 903. All the core(s) 921 included in the CPU 902 execute(s) the boot firmware program stored in the SDRAM 903. The SDRAM 903 is hereafter used as a storage area of the boot firmware program and a storage area of data at boot time. The hardware other than the service processor 901, the CPU 902, the SDRAM 903, or the boot ROM 904 is then initialized. The CPU 902 reads an OS (Operating System) boot loader for I/O (Input/Output) devices, and starts to execute the read OS boot loader.
As a method for booting a computer, there is a conventional technique in which a baseboard management controller loads firmware from a memory, stores the firmware into a cache memory, and performs a boot. There is a conventional technique in which a CPU reads and stores a boot firmware program into a cache memory, and performs a boot. There is a conventional technique in which a processor for diagnosing a server computer copies a boot firmware program to a main memory device and performs a boot.
Patent Document 1: Japanese National Publication of International Patent Application No. 2006-515940
Patent Document 2: Japanese Laid-open Patent Publication No. 2008-16020
Patent Document 3: Japanese Laid-open Patent Publication No. 2009-217336
However, the conventional information processing apparatuses are provided with the boot ROM in which the boot firmware program used for booting is stored. This increases the product cost.
Even with the conventional techniques of reading the boot firmware program into a cache memory or a main storage device, the provision of the boot ROM or other storage devices containing the boot firmware program makes it difficult to reduce the product cost.